The present invention relates to pulse-width-modulated (PWM) signals.
Pulse-width-modulated signals are useful, for example, for the control of asynchronous motors or inverters used in household appliances, ventilation air control systems, pumping systems and the like. A pulse-width-modulated signal SC (FIG. 1c) is a cyclical signal that is activated periodically (Ai, Ai+1), and deactivated at variable points in time (Di, Di+1) between two operations of activation. The time TC between two operations of activation is called a switching period. The ratio TC1/TC between the duration of the active signal and the switching period is called a cyclical ratio. The signal SC may be active at 0 or at 1.
When a pulse-width-modulated signal is used to control an asynchronous motor, the variations in time of the cyclical ratio of the control signal lead to similar variations in current in the phase or phases of the motor. For example, with an appropriate control signal SC, sinusoidal variations of the current can be obtained in the phase or phases of the motor.
A pulse-width-modulated signal SC is conventionally obtained by a generator that produces the signal SC from a reference signal SREF which is a sampled analog signal. The initial analog signal may have a sine (FIG. 1a), trapezoidal, square or any other shape. The sample reference signal SREF (FIG. 1b) is obtained by the sampling of the initial analog signal. It comprises a set of binary numbers E0 to ENBECH whose value depends on the amplitude of the signal at the instant considered. The smallest value of the numbers E0 to ENBECH, for example, equal to 0, is associated with the sample having the smallest amplitude. Conversely, the highest value of the numbers E0 to ENBECH is associated with the greatest amplitude of the initial signal.
The number of signals chosen NBECH is a compromise between the desired precision (which increases with the number of samples) and the computation time needed to obtain the signal SC from the sampled reference signal SREF (which also increases with the number of samples). For example, in the case of an initial sine analog signal, it could be chosen to take 360 samples, i.e., every 10 on a period TREF=360xc2x0 of the analog signal, or else 2N samples every TREF/2N on a period TREF of the analog signal, with N being the size of a register of the circuit.
A known generator of pulse-width-modulated signals is shown in FIG. 2. The generator has a counter CPC, a reference memory MR, a comparison register RC and a comparator CPT. The numbers E0 to ENBECH are stored in the reference memory MR of the generator. The M-bit counter CPC counts pulses of a clock signal CP and gives a number of counted pulses NB varying between 0 and NBMAX=2Mxe2x88x921. When the number NBMAX is reached, the counter returns to zero and then starts counting again.
The samples E0 to ENBCH of the sampled reference signal SREF contained in the reference memory MR are successively loaded into the comparison register RC. A sample Ei is loaded at each return to zero of the counter CPC. As the case may be, the same sample Ei may be loaded several times successively. In every case, a loading is done at each return of the counter to zero.
The comparator CPT continuously compares the number NB given by the counter with the sample Ei contained in the comparison register RC. The comparator CPT gives the control signal SC having the following properties. For every value of i ranging from 0 to NBECH, SC is active when NB less than Ei, and SC is inactive when NBxe2x89xa7Ei.
FIG. 1c shows the development of the number NB, the samples Ei and the signal SC resulting in one example. The signal SC is active at 1 and inactive at 0. The signal SC is thus activated at each return to zero of the counter, and then deactivated when the number NB given by the counter exceeds the value Ei of the sample contained in the comparison register RC.
Referring to FIG. 1C, a pulse signal is obtained. In this signal, the width of the active pulses (and hence the cyclical ratio) varies in time as a function of the value Ei of the samples of the reference signal SREF, and hence as a function of the initial analog signal. The precision of the generator depends on the range of variation of the cyclical ratio and on the minimum variation of the cyclical ratio.
The cyclical ratio R of the control signal SC can be computed as follows. For each period TC of the counter (since the signal SC is activated at each return to 0 of the counter):                     R        =                              (                                          E                i                *                            ⁢              TCP                        )                    /                      (            TC            )                                                  =                              (                                          E                i                *                            ⁢              TCP                        )                    /                      (                                                            (                                      NBMAX                    +                    1                                    )                                *                            ⁢              TCP                        )                                                  =                              E            i                    /                                    (                              NBMAX                +                1                            )                        .                              
NBMAX=2Mxe2x88x921 is the maximum value of the number NB, M is the size of the counter, and TCP is the period of the clock signal CP.
The minimum variation in the cyclical ratio is equal to xcex94Rmin=1/(NBMAX+1). The precision of the generator is directly proportional to the number NBMAX, namely the size of the counter. The precision of the generator increases also with the range of variation of the cyclical ratio. It is preferable to have available a generator producing control signals whose cyclical ratio varies from 0 to 100% to have as wide a range of control as possible. In this way, unnecessary losses and deterioration are avoided in the electronic control circuits of the motor.
The minimum value Rmin of the cyclical ration is equal to 0%. This corresponds to Ei=0.
The maximum value of the cyclical ratio is equal to:
Rmax=X/(NBMAX+1).
X is the maximum value of the numbers E0 to ENBCH. Rmax can reach 100% only if X can reach the value NBMAX+1=2M, with M being the size of the counter. To attain a cyclical ratio of 100%, the numbers E0 to ENBCH should be encoded on a number of bits at least equal to M+1 to be able to reach the value 2M.
If the register RC used has a size N (for example, N=16) greater than the size M (for example, M=12) of the counter CPC, this does not raise any problems. It is possible to use 13-bit numbers Ei which are loaded into the register RC and then are compared with the 12-bit numbers NB given by the counter. It is also possible to use 16-bit numbers Ei (enabling higher precision to be obtained on the sampled signal). These numbers are loaded into the register RC, and only the 13 most significant bits of the numbers Ei are compared with the 12-bit numbers NB given by the counter CPC.
A problem arises, however, when the registers and the counter have an identical size. A first known approach uses two comparison registers, the first to store the N least significant bits of the numbers E0 to ENBCH, and the second to store the most significant bits of these numbers. This approach, however, is not worthwhile because it implies the loading of two registers at each return of the counter to zero. This increases the time for loading the numbers Ei, and therefore the time for computing the signal SC. Furthermore, the size of the circuit is increased.
In a second approach, only the Mxe2x88x921 least significant bits of the counter CPC are used to produce the Mxe2x88x921 bit numbers NB, and the register RC sized N=M is used to store the numbers E0 to ENBCH. It is thus possible to attain a cyclical ratio Rmax equal to 100%. This approach, however, is not worthwhile because it impairs the performance of the generator by reducing its precision (the number xcex94Rmin increases).
Thus, if the registers and the counter of the generator are identical in size, it is not possible, with the prior art approaches, to obtain an optimum generator that has both maximum precision and minimum computation time.
In view of the foregoing background, an object of the present invention to provide an optimized generator making the most efficient use of the capacities of its components while at the same time maintaining high precision and limited computation time.
This and other objects, advantages and features according to the present invention are provided by a method for the generation of a pulse-width-modulated signal out of a sampled reference signal, a method in which a counter is incremented to produce numbers NB incremented at each pulse of a clock signal. A reference number is updated each time the counter reaches a setting value. The reference number relates to the reference signal.
According to the method of the invention, the following steps are also performed. An overflow bit is computed by comparing a pointer value with a reference parameter. The pointer value is updated each time the counter reaches the setting value. The control signal is produced by comparing a number NB given by the counter with an updated comparison word comprising the overflow bit in terms of the most significant bits, and the updated reference number in terms of the least significant bits.
The invention also relates to an associated generator of pulse-width-modulated signals. The generator comprises a counter to count the pulses of the clock signal and provide the numbers NB. A comparison register stores the reference number.
According to the invention, the generator also comprises a test circuit to compute the overflow bit, and an overflow register to store the overflow bit. A comparator gives the control signal by comparing the number NB given by the counter with the updated comparison word comprising the overflow bit in terms of most significant bits and the updated reference number in terms of least significant bits.
The numbers NB given by the counter and the updated reference number are of the same size N. The updated comparison word is a sample of the reference signal associated with the value of the updated pointer. The pointer indicates the sampling times. The updated reference number is obtained by eliminating the most significant bit of the sample of the reference signal associated with the updated pointer value.
According to one variation, the reference parameter is a pointer value for which the associated sample of the reference signal has maximum amplitude. According to another variation, the reference parameter is a set comprising several pointer values. The sample of the reference signal associated with each of the pointer values has a maximum amplitude.
In general, as will be seen more clearly below, the reference parameter is chosen as a function of the following. The number of samples of the reference signal, the type of increment used to update the pointer value, and the shape of the initial analog signal.
Thus, with the invention, the N least significant bits of a sample of the reference signal are stored in the comparison register. At the same time, it is verified in a test circuit that the sample considered corresponds to maximum amplitude of the reference signal and, if this is the case, an overflow bit is given. The overflow bit and the N least significant bits of the sample considered are then linked together to obtain the comparison word. The comparison word is then compared with the number NB given by the counter.
Thus, when the counter and the comparison register have the same size, it is possible with the invention to use all the bits of the counter without its being necessary to use two comparison registers to store the sample of the reference signal.
According to one embodiment of the generator, the test circuit comprises a comparator with two inputs to which the reference parameter and the updated pointer value are applied respectively, and an output is connected to the overflow register. According to another embodiment, the test circuit comprises software means to compare the reference parameter with the updated pointer value.
The generator described above may be used to control a monophase device, for example, of the motor or inverter type. If the device is a triphase device, the invention will preferably use a control circuit comprising three generators as described above, operating in parallel but preferably using a single common counter.